There already exist test methods for electronic integrated circuits that make it possible to measure their quality and reliability so as to increase their production yield.
For example, a known technique for testing integrated circuits, illustrated in FIG. 1, consists of connecting all the registers (sequences, counters, RAM (Random Access Memory) etc) present in a chip or integrated electronic circuit, by means of a “scanline” (the output of a register being connected to the input of the following register), and then operating the circuit in order to observe the final state after interruption of its functioning at a predefined time.
The state of the circuit is then obtained by “scanning” all the registers (denoted R1 . . . R7), that is to say by emptying them one after the other (via the “scanline”), in order to obtain a series of states. This series of states is then compared with a reference series of states, expected for the circuit being tested.
A major drawback of this technique lies in the fact that connecting all the registers requires the use of a lot of resources and complex implementation, requiring dedicated connection technology.
In addition, the “scanline” linking all the registers separates the circuit into two parts and makes installing elementary components in this circuit more complex, preventing certain connections between components situated on each side of this link (or requires the use of dedicated means (“bridges”) to pass over this link, or “boundary”, between the two parts).